Channel & Physical Interface Configuration

• I/O Channel Partition: 96 identical 3.3 V LVTTL digital I/O lines; 64 lines via detachable screw terminal blocks, 32 lines via 100-mil standard pitch plated through holes
• Mezzanine Interface: Standard RMC (Reconfigurable Mezzanine Card) edge connector, pin-to-pin compatible with all 2nd/3rd generation sbRIO backplane interfaces
• Front Status Indicators: Independent power LED for 3.3 V FPGA rail and 5 V auxiliary rail, no per-channel I/O activity indicators
• Physical Dimensions: 92 × 65 mm PCB footprint, 82 g bare board weight without terminal accessories
• Mounting Form: Stackable vertical stacking installation, supports 4-layer multi-board stacking with spacer accessories

Core 3.3V LVTTL Digital I/O Electrical Parameters

• Input Logic Threshold: VIL 0–0.8 V (logic low), VIH 2.0–3.465 V (logic high), strict 1.2 V hysteresis noise margin
• Per-Channel Current Rating: ±3 mA continuous sink/source current, no parallel overcurrent support for single pin
• Total Bank Current Limit: 288 mA aggregate maximum current for all 96 I/O lines simultaneous operation
• Output Voltage Performance: VOH ≥2.4 V @ 3 mA sourcing; VOL ≤0.4 V @ 3 mA sinking at 25 ℃ ambient temperature
• Input Impedance: 10 kΩ internal weak pull-down resistor on all idle I/O pins to avoid floating signal drift
• Switching Speed: Maximum 10 MHz deterministic toggle frequency matched with sbRIO FPGA timing clock

Onboard Regulated Auxiliary Power Output

• FPGA 3.3 V VIO Rail: 0.33 A continuous output capacity, ±5% output voltage tolerance, dedicated for low-power external logic chips
• 5 V Auxiliary Rail: 1.5 A continuous regulated output, ±5% voltage tolerance, for proximity sensors and indicator lamps
• Overcurrent Protection: Independent resettable surface-mount fuses for both power rails, automatic power cut-off within 20 ms under short-circuit fault
• Isolation Grade: Non-galvanic isolation between auxiliary power and sbRIO host backplane, common ground design

Timing & Synchronization Specifications

• FPGA Deterministic Latency: <150 ns round-trip I/O response latency via RMC mezzanine bus
• Synchronization Mode: Native synchronous timing with sbRIO onboard 40 MHz FPGA oscillator, no external trigger wiring required
• Cross-Channel Skew: <25 ns skew across all 96 channels during parallel simultaneous switching
• Glitch Suppression: Hardware input deglitch circuit with fixed 40 ns filter window to eliminate transient EMI noise

Environmental & Ruggedized Specifications

• Operating Temperature: -40 ℃ ~ +85 ℃ full-temperature operational range, no performance derating at extreme boundaries
• Storage Temperature: -55 ℃ ~ +100 ℃ for long-term warehouse and transportation storage
• Humidity Rating: 10%–90% non-condensing for operation, 5%–95% non-condensing for storage
• Shock Resistance: 50 g half-sine operational shock compliant with MIL-STD-810G
• Vibration Resistance: 0.52 grms random vibration for airborne and vehicle-mounted scenarios
• Safety & EMC: IEC 61010-1 Pollution Degree 2, CE/FCC Class B indoor EMC certification

Compatibility Matching List

• Compatible Host Controllers: sbRIO-9606, sbRIO-9627, sbRIO-9651 all second-generation RMC-based single-board RIO devices
• Incompatible Devices: PXI/PXIe series modules, C-series compactDAQ modules, legacy RIO non-RMC controllers
• Matching Accessories: Phoenix 12-position screw terminal plugs, 100-mil jumper pin headers, plastic stacking spacers
• Official Status: Active production model, no end-of-life announcement, permanent official repair and spare part support

Software Compatibility

• Required Drivers: NI-RIO core driver, NI-DAQmx embedded runtime, no additional dedicated breakout driver needed
• Configuration Tools: NI MAX, RIO Device Configuration Utility, FPGA I/O Mapping Editor
• Development Software: LabVIEW Real-Time, LabVIEW FPGA, C API for embedded Linux deployment
• Supported OS: NI Linux Real-Time, Windows 10/11 remote development hosts, no Phar Lap ETS support

Pros & Limitations

• Pros: High-density 96-channel compact expansion, dual-form wiring interface for flexible integration, ultra-wide rugged temperature range, built-in fused auxiliary power, FPGA-grade deterministic low latency, lightweight stackable structure for limited enclosure space
• Limitations: No channel-to-backplane galvanic isolation requiring external isolated terminals, only 3 mA weak drive unable to directly drive relays, exclusive RMC interface incompatible with standard PXI systems, no differential I/O support